1. Field of the Invention
The present invention relates to a multi-port network interface circuit and a related method, and more particularly, to a multi-port network interface circuit and a related method for scrambling signals of different ports with different seeds, and making the data transitions of different ports asynchronous by adopting different reset times.
2. Description of the Prior Art
In the modern information age, the Internet, capable of exchanging information, data, and knowledge efficiently, is becoming a very popular tool to develop new technologies and to improve relations among people. That is why it has become a major concern for the information industry as well as governments to develop facilities related to the Internet as fast and thoroughly as possible.
A variety of network connection topologies have been used to build networks formed with a plurality of terminals. Each of the terminals in these topologies can be deemed as a node of the network and connections between these nodes, directly and indirectly, make up the network. For example, 10 BASE T and 100 BASE T, two popular patterns of local area networks, both adopt a star-structured topology to build a network, each of the terminals connecting to the rest of the nodes or to another network device (hubs, switches, or routers) via a hub or a switch to form a network and to exchange data with network-related devices in the network. In other words, network-related devices, such as hubs, switches, and routers, interconnect with the nodes (terminals) to form a network so that users of any terminal can access data of the rest of the terminals via the network.
These network-related devices used to interconnect the nodes in the network usually contain network connection ports, each network connection port being connected to only one node or other network device. These network devices can, therefore, transmit data signals with a network interface circuit to each of the network nodes via a corresponding network connection port and receive data transmitted from the network nodes, thus realizing internetwork connection. Please refer to FIG. 1, which is a functional block diagram of a conventional multiple-port network interface circuit 10. The network interface circuit 10 can be a network interface circuit utilized in a network device, such as a hub, a switch, or a router. The network interface circuit 10 includes a MAC (Medium Access Control) circuit 12 for transmitting and receiving signals to and from many nodes with a plurality of multi-port PHY circuits. For simplification, in the representative example in FIG. 1, it is assumed that there are two PHY circuits, 14A and 14B, each able to exchange information with two nodes (terminals) such that the network interface circuit 10 is capable of exchanging information with 4 nodes, 24A to 24D, respectively and simultaneously. It is practical in the modern network interface circuit to combine three eight-port PHY circuits to realize a 24-port network interface circuit.
In the network interface circuit 10, the MAC circuit 12 is used to control the signal transmission of each PHY circuit to each node for realizing the function of the MAC layer under the OSI (Open System Interconnection) structure, and the PHY circuits 14A and 14B are utilized to realize the function of the PHY layer. The data to be transmitted to node 24A to 24D is packeted by the MAC circuit 12 and transmitted to the PHY circuit 14A and 14B through four output ports, Ep1 to Ep4. As shown in FIG. 1, scramblers 16A to 16D and encoders 18A to 18D are included in the PHY circuit 14A and 14B for processing the packets that are to be transmitted to the node 24A to 24D. In addition, the signals coming back from the node 24A to 24D are transmitted to the network interface circuit 10 through input ports 22A to 22D to receivers 30A and 30B, and further transmitted back to the MAC circuit 12 after being processed by the receivers 30A and 30B. When realizing the network interface circuit 10 in FIG. 1, the signals are differentially transmitted to corresponding nodes in twisted pair lines. Similarly, each node transmits the data back to a corresponding input port of the network interface circuit 10 in differential manner (such as opposite phase). In addition to transmitting and receiving signals to and from the nodes 24A to 24D through the PHY circuits 14A and 14B, the MAC circuit 12 controls the function of the PHY circuits 14A and 14B by sending commands to control ports CL1 and CL2 of the PHY circuits 14A and 14B. Further provided are reset ends RS1 and RS2, in the PHY circuits 14A and 14B respectively. As illustrated in FIG. 1, a reset circuit 26 triggers the reset signal of the PHY circuits 14A and 14B simultaneously to initialize the control course, the state machine, and the data in the registers and restart the function of the network interface circuit 10.
The operation of the network interface circuit 10 can be further described as follows. For example, if there is data to transmit to the node 24A by the MAC circuit 12, the MAC circuit 12 appends information such as a header, a MAC address, and an error checking code to a packet of the data. This packet is then transmitted as a signal Mp1 to the scrambler 16A in the PHY circuit 14A through the output port Ep1. The scrambler 16A has a random number generator 32A which chooses a seed among a plurality of seeds from Sp(1) to Sp(N) to generate a scrambling code Sc0, and the scrambler 16A executes a logic operation OP0 on Sc0 and MP1 to produce a scrambled signal Np1. The scrambled signal Np1 is further transmitted to an encoder 18A to be encoded, modulated, or amplified by the encoder 18A. The output signal Kp1 of the encoder 18A is transmitted to the node 24A through an output port 20A. The signals transmitted by the node 24A through the input port 22A are received, demodulated, decoded, and de-scrambled to the original packets by the receiving circuit 30A, and then transmitted back to the MAC circuit 12 and de-packeted by it. Similarly, the scramblers 16B to 16D execute the logic operation OP0 with scrambling codes generated by corresponding random number generators 32B to 32D respectively and packets Mp2 to Mp4 which are to be transmitted to nodes 24B to 24D to generate the signals Np2 to Np4 separately. After scrambling, the signals Np2 to Np4 are then encoded by the encoders 18B to 18D and are transmitted to corresponding nodes 24B to 24D.
In the network interface circuit 10, when exchanging data with a node, such as node 24A for example, the scrambler 16A changes the seed adopted by the random number generator 32A at every predetermined period. For example, at a certain moment, the random number generator 32A adopts the seed Sp(1) to generate the scrambling code Sc0 to scramble the signal Mp1. After the predetermined time, the random number generator 32A adopts the seed Sp(2) to generate the scrambling code Sc0. And after another predetermined period, the random number generator 32A adopts the seed Sp(3) to generate the scrambling code Sc0. The seeds are adopted in turn like this. After the last seed Sp(N) is adopted, the random number generator 32A reuses the seeds in turn again. Please refer to FIG. 2. The scrambler 16A in FIG. 1 is taken as an example here to illustrate the function of each scrambler in the network interface circuit 10. In the scrambler 16A, the random number generator 32A uses a plurality of registers 34 to temporarily store the bits of a seed, seed Sp(n) for example, and executes a shifting and exclusive OR operation 36 to generate the scrambling code Sc0. The scrambling code Sc0 is then affected by the logic operation OP0 with the signal Mp1 for generating the scrambled signal Np1. The signal Np1 is then encoded by the encoder 18A to produce the corresponding signal Kp1.
Please refer to FIG. 1 again. When the encoded and scrambled signal Kp1 is received by the node 24A, it is first decoded, that is, recovered to the signal Np1, and then descrambled, that is, recovered to the signal Mp1, for recovering to the transmission packets to the node 24A from the network interface circuit 10. There are established standards for encoding and decoding in the network protocol. As long as the two sides of the network connection adopt the same network protocol, the encoded signals can be decoded successfully. The standard of the operation of the random number generator 32A, the logic operation OP0, and the values of the seed Sp(1) to Sp(N) are also given by the network protocol. However, the receiver does not know what seed the transmitter adopts for generating the scrambling code. For example, when the network interface circuit 10 starts to transmit signals to the node 24A, it may start from the seed Sp(2) to generate the scrambling code Sc0, and change the seed at every predetermined period. Since the network interface circuit 10 does not notify the node 24A which seed the scrambler 16A uses, the node 24A is not able to de-scramble the scrambled signals. The network interface circuit 10 has to establish a link with the node 24A so the node 24A can de-scramble the signals successfully. For the purpose above, the MAC circuit 12 takes a predetermined idle pattern signal, for example, a predetermined number of successive 0s, as the signal Mp1. The signal Mp1 is scrambled, encoded, and then transmitted to the node 24A. According to the network protocol, the node 24A knows the first transmitted signal is the idle pattern signal, and it knows the content of the idle pattern signal. Therefore, the node 24A can recover the seed adopted by the scrambler of the network interface circuit 10. Knowing the seed adopted by the scrambler 16A, the node 24A can descramble the signal Np1 to the signal Mp1 and recover the packet transmitted by the network interface circuit 10. After a predetermined period, the scrambler 16A will use the next seed for scrambling, and the node 24A knows what the next seed is by the network protocol. In addition to sending the idle pattern data, the two sides of the network connection recognize the transmission status, like whether the link is shut down or not, by sending the idle pattern signals during transmission. In the conventional network interface circuit 10, each of the scramblers 16A to 16D starts with the same seed Sp(1), and the order of the seed sequence is the same.
In the network interface circuit, the purposes of scrambling and encoding are making the electrical characteristics of the transmission signal better. In a network, especially an area network, the DC part of the transmission signals is filtered during the transmission. The waveforms of successive 0 or 1 bit data in the transmission signal, such as “00000000” or “11111111”, are a successive straight lines with different DC levels. For instance, the waveform of eight successive 0s is a low level DC signal continuing for eight clock cycles, and the waveform of eight successive 1s is a high level DC signal continuing for eight clock cycles. Once the DC part is filtered during the transmission, the high level DC signal is filtered out and the receiver can no longer ascertain whether the received signals are successive 0s or 1s. This is so-called baseline wander. To avoid the successive 0s or 1s in the transmission signal, scrambling and encoding are adopted before transmitting the signals to interlace the 0 and 1 bit data.
Please refer to FIG. 3 and FIG. 1. FIG. 3 is the timing diagram of the related signals of the operation of the network interface circuit 10 shown in FIG. 1. The X dimension is time, and the Y dimension the amplitude of the waves. Generally speaking, the control process, the state machine, and the registers are initialized whenever a sequential logic circuit starts to operate. When the network interface circuit 10 in FIG. 1 starts to operate, the reset circuit 26 sends a signal 28 to reset and initialize the PHY circuits 14A and 14B simultaneously. For example, the scrambler 16A to 16D starts to scramble with the seed Sp(1) uniformly. As illustrated in FIG. 3, since the PHY circuits 14A and 14B are reset to start operation at the same time, the signals Mp1 to Mp4 are scrambled by the scramblers 16A to 16D simultaneously. Therefore, the data transition times of the signal Mp1 to Mp4 are all equal. For instance, as demonstrated in FIG. 3, the signals Mp1 and Mp2 change from a digital 1 to a 0 at tp0, and the signals Mp3 and Mp4 change from a digital 0 to a 1 at tp1, etc. Besides, as described above, the network interface circuit 10 sends fixed idle pattern signals to each node when the links are established or re-recognized. So, it is very possible that the signals transmitted from the MAC circuit 12 to the scramblers 16A to 16D are the same during these times, as shown by the signals Mp1 to Mp4 in FIG. 3 before tp0.
Though the successive 0s or 1s in the scrambled signals Np1 to Np4 will be scattered after scrambling, the data transition times of signals Np1 to Np4 are still the same because the signals Mp1 to Mp4 are identical before time tp0, and the initial seeds of the scramblers 16A to 16D are equal in the conventional network interface circuit 10. For example, the signals Np1 to Np4 change from a digital 0 to a 1 at time tp3 simultaneously. The signals Np1 to Np4 are encoded to the signals Kp1 to Kp4 by the encoders 18A to 18D respectively. Since the signals Np1 to Np4 are equal before time tp0, the encoded signals Kp1 to Kp4 are identical, too. Because of the same reset time of the PHY circuits 14A and 14B, the data transition times of the signals Kp1 to Kp4 are equal. For instance, at time tp5, the bit data of the signals Kp1 to Kp4 change from 0 to 1 simultaneously, and further, from 0 to 1 at time tp6 simultaneously.
Power is needed to drive the data transition for scrambling, encoding, or transmitting signals through the network transmission line to the remote node. For example, the DC biasing source of the network interface circuit 10 has to drive the output load to pull up the output signal level when the output signal changes from a low level to a high level. Similarly, the DC biasing source has to pull down the output load to the ground of the network interface circuit 10 to pull down the output signal level when the output signal changes from a high level to a low level. In other words, the current of the DC biasing source or the discharging current to the ground has to be increased when a circuit drives the data transition of the signal. On the contrary, the power consumption and the current are decreased dramatically when the signal level is maintained after the data transition. For the network interface circuit, the scramblers and the encoders ask for more charging or discharging current at the data transition. However, in a conventional network interface circuit 10, the data transitions of the signals Np1 to Np4, Kp1 to Kp4 are at the same time, and it is very possible that the transmitted data of the signals are equal because the scrambling seeds of each port are the same. So, the total power consumption and the current of the PHY circuits 14A and 14B increase simultaneously. This substantially increases the need of DC biasing current and discharging current to ground resulting in power bounce. In general, the network interface circuit 10 uses an external DC biasing source to provide power. If all the circuits in the network interface circuit 10 require an increase in power for simultaneously driving the same kind of data transition, the external DC biasing source is unable to answer the request immediately and smoothly and hence a ripple response results. Therefore, the DC biasing source is unable to supply the current stably, and the quality of the network interface circuit 10 operation is reduced. Likewise, if discharging currents to the ground for each circuit increase simultaneously, the potential of the ground may be changed by the current impulse causing the bias of the transistors in the network interface circuit 10 to drift such that inappropriate operation may appear.
In addition to power bounce, the simultaneous data transitions of the conventional network interface circuit 10 cause cross talk among the transmission lines. For example, when the signals Kp2 and Kp3 are simultaneously pulled up to the high level at time tp5, some part of the energy of the signal Kp2 may couple to the signal Kp3 because of the constructive electrical coupling between the circuits 16A and 16B (or say the electrical coupling caused by the equal phase), so the level of the signal Kp3 may be raised higher than the level of a digital 1, as the dotted line 37a illustrates in FIG. 3. In other words, after reaching the predetermined level of a digital 1, the level of the signal Kp3 keeps increasing and may exceed the upper limit of the signal level and damage the circuit. Similarly, at time tp7, the signal Kp2 changes from the low level to the high level and the signal Kp3 changes from high to low simultaneously. The signal Kp3 may not be capable of reaching a level which is low enough to represent the digital 0 or may require longer time to reach the predetermined low level when it changes from high to low because some part of the increased energy of the signal Kp2 couples to the signal Kp3, as the dotted line 37c illustrates. On the contrary, the signal Kp2 may be not capable of reaching the predetermined high level or may take a longer time to reach it because some part of its increased energy couples to the signal Kp3, as the dotted line 37b illustrates. Once there are distortion and delay in the waveforms of the signals Kp1 to Kp4 as described above, erroneous judgment of the data and problems in synchronization of the signals follow.
To sum up, for a conventional multi-port network interface circuit 10, the PHY circuits are reset simultaneously and start to operate at the same time, and each scrambler in the PHY circuits starts with the same seed so that data transitions happen at the same time. This causes power bounce and cross talk, and therefore, unstable power and distortion of the signal waveforms. This is even more serious in current networks since speed of data transmission is higher and the number of transmitted data bits is increased meaning the transitions in a unit of time unit are also increased. This causes the time margin of the conventional network interface circuit 10 for recovering from power bounce to be shorter, and the problem of the power bounce, electrical coupling, and the distortion of the waveform to be more severe.